From “Available” to “Practical”: Architectural Framework and Industrial Practice of the Software Ecosystem for Domestic AI Chips

Against the backdrop of intensified international technological competition and explosive growth in demand for AI computing power, domestic AI chips have made significant progress in hardware performance. Meanwhile, users’ concerns have shifted from mere availability to maturity, compatibility, and usability of the software ecosystem. As a key factor in unlocking chip value, the software ecosystem directly determines the commercialization and market competitiveness of AI chips. This article systematically reviews the current development status of the software ecosystem for domestic AI chips and proposes a four-layer architectural framework consisting of the foundational support layer, core tool layer, framework adaptation layer, and management and monitoring layer. It further analyzes the core functions, supporting technologies, and industrial practices at each layer. By conducting a comparative study of representative domestic vendors, including Huawei Ascend, Moore Threads, Cambricon, MetaX, and Hygon, in terms of software stack resources, CUDA compatibility, and community activity, this article reveals that two mainstream development paths—namely the “full-stack ecosystem” and the “compatibility ecosystem”—have gradually emerged, together with a differentiated competition pattern driven by application scenarios. The study shows that the software ecosystem of domestic AI chips has evolved from “basically available” to “practical in specific scenarios”. However, compared with international mainstream ecosystems, there are still gaps in toolchain completeness, ecosystem maturity, and developer base. This article aims to provide an objective reference for industrial selection, technological research and development, and policy making, and to support the further advancement of domestic AI chip ecosystems from “practical” to “excellent”.